Designing an ASIC can be a game-changer for your business, and we at Lucid IDM can help you design and produce the right ASIC solution for your next product.
System Architecture Definition
Definition of the ASIC Architecture to meet the customer’s system requirements
System Level and SoC microarchitecture development
HW and SW partitioning to generate a balanced solution
System level SoC verification in the early stages of the definition using ESL SystemC modelling.
IP & SoC Verification
System level SoC verification in the early stages of the definition using ESL SystemC modelling.Verification
Module/top level SoC verification
Verification with advanced methodologies (Specman/SystemVerilog/SystemC)
e-based/SystemVerilog random and constraint driven verification
Verification Expertise in UVM – Universal Verification Methodology
Formal verification
Functional coverage analysis
Mixed signal verification
Gate Level verification including SDF
Design
High Level Design
Micro Architecture Documentation
RTL Coding with VHDL or Verilog
Low power awareness technics
Synthesis and Backend
Floor planning
Synthesis and DFT insertion
P&R and timing closure
Cadence and Synopsys tools
Low power optimization
P&R and timing closure
Timing and SI-aware place and route
Full-chip RCextraction
Full-chip timing/SI closure, static timing analysis and sign-off
Full-chip physical verification (DRC)
Full chip Logic Vs Schematic verification (LVS)
Chip finishing and Tape-Out
Automatic Test Pattern Generation (ATPG)
Cadence and Synopsys tools
SoC Post Silicon Validation
Firmware development team
Board design services
Performance analysis and validation
Let's Talk About Work
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